In a semiconductor manufacturing, chemical mechanical polishing (CMP) is designed to polish a substrate and to provide a global planarized surface. The CMP process can be implemented at various integrated circuit (IC) fabrication stages, such as a shallow trench isolation (STI) process and a dual damascene process.
In STI, a nitride or other CMP resistant layer is deposited onto a silicon wafer, after which shallow trenches are etched into wafer. Several islands of nitride are left, which are later to become the locations of active areas (transistors, etc.). The trenches are then filled with oxide to form the dielectric areas. After that, the planarization of the wafer needs to be performed a CMP process, in order to acquire optimal gate patterning later on.
However, because the removal rates of metal and dielectric materials are usually different, polishing selectivity leads to undesirable dishing and erosion effects. Dishing often occurs when the metal recedes below or protrudes above the level of the adjacent dielectric. Erosion is a localized thinning of the dielectric. Dishing and erosion are sensitive to pattern structure and pattern density.
For example, STI uses CMP to form a global planarized profile. Over-etching is typically performed to ensure a complete etch of the silicon oxide on silicon nitride. Surface variations associated with local pattern and pattern density may be eliminated by the use of dummy features such as dummy active features in STI trench. Dummy features formed by conventional methods may enhance pattern spatial signature, but may not effectively compensate step height variation.